1. Field of the Invention
The present invention relates to a package for encapsulating a semiconductor integrated circuit (IC) and, more particularly, to an improvement in package for a dynamic random access memory (DRAM) having a large memory capacity.
2. Description of the Prior Art
With increase of integration density of an IC, a chip area is increased. For example, a DRAM of 1 M-bit has at least 5 mm wide and at least 10 mm long. Although the increase in chip area of a DRAM is being suppressed by improving the miniaturization technology, it would be unavoidable that the chip area is made large with the memory capacity being increased to 4 M-bit, 16 M-bit and so forth.
For an IC such as 256 K-bit DRAM which has an intermediary integration density and an intermediary chip area, a plurality of chip terminals, that is, wire bonding pads, formed on a chip are generally arranged linearly along peripheral edges of the chip (in general, along a pair of long sides of the rectangular chip). The chip is mounted on a chip mounting portion of a lead frame which has a plurality of leads extending radially from the chip mounting portion. The chip terminals and inner end portions of the respective leads are connected through thin gold wires (i.e., bonding wires), respectively. The above-mentioned positional relation among the chip, the leads and the bonding wires is similar to that in a ceramic package whose chip mounting portion and leads are formed by a metallized layer on an insulator substrate.
In the IC package mentioned above, end portions of the respective leads, that is, inner end portions thereof, are positioned outside the chip mounting portion. Therefore, the package size is increased correspondingly. Further, since the inner end. portions of the lead fingers on which the wires are bonded constitute root portions of the lead fingers after the chip is encapsulated by resin molding, and thus are required to withstand stress applied thereto. To this end, the respective inner end portions have marginal parts in a plane of the chip, each being wide enough to absorb such stress. Such marginal parts would prevent miniaturization of IC package. Although increase of package size caused by such marginal parts may be not considerable for an IC whose chip area is small, an increase of chip area and an increase of the number of terminals caused by increase of integration density would increase the package size considerably, further preventing miniaturization of a device including such ICs.
In order to solve this problem, IBM corporation announced, in 1988, an IC package (A-wire package) called "area wire bond" for 1 Mbit DRAM. (This package is disclosed in detail in U.S. Pat. No. 4,862,245 issued on Aug. 29, 1989 and further in, "Volume Production of Unique Plastic Surface-Mount Modules for the IBM 80-ns 1-Mbit DRAM Chip by Area Wire Bond Techniques", Proceedings of the 38th Electronic Component Conference, XIII-4, May, 1988, pp. 552-557).
This A-wire package is featured in that chip terminals on a rectangular memory chip are arranged in a longitudinal center portion of the chip and further in peripheral portions along short sides thereof, contrary to the conventional arrangement in which chip terminals are arranged on peripheral portions along the long sides. Further in this package, the chip mounting portion which would be required in the conventional package is removed, and the leads are arranged on the chip surface through an insulating film such that inner end portions of the respective leads are positioned inside a rectangular periphery of the chip. Since, in such A-wire package, connections between the chip terminals and the inner end portions of the lead fingers using the thin metal wires are formed in a plane which is in parallel to the chip and has a smaller area than that of the chip itself, the size of the package is made small to be substantially the same as that of the rectangular chip and therefore there is no protrusion of root portions of the lead fingers from the peripheral portion of the chip, that is, there is no protrusion of the inner end portions for wire bonding and stress absorbing margin, etc. Further, since the connections between the chip terminals and the inner end portions of the leads are fixedly formed on a surface of an insulating film of such as polyimide resin covering the surface of the chip, absorption of stress exerted from the outer end portions of the leads can be achieved easily. Further, since it is possible to reduce distance between the chip terminals and the inner end portions of the lead fingers, an amount of thin gold wires necessary to connect them can be saved.
However, in the A-wire package, a pair of busbars are required to be formed in positions corresponding to the arrangement of the chip terminals in the longitudinal center portion of the rectangular chip and inside the inner end portions of the lead fingers of the lead frame, the busbars being used to supply a source voltage and a ground potential to predetermined chip terminals through the thin gold wires. Therefore, the bonding wires, which connect some chip terminals for signal sources other than the voltage source and the ground potential source to the corresponding inner end portions of the leads are required to overarch the busbars. The thin gold wires overarching the busbars may be deformed during a pressure injection of resin material in a mold step for package formation, resulting in short-circuit with the busbars. Further, such overarching gold wires may increase thickness of the package.